ENGR210.github.io

Welcome to ENGR 210 ( CSCI B441 )

Spring 2019

This course provides a strong foundation for modern digital system design using hardware description languages. We start with basics of digital electronics and learn how digital gates are used to build large digital systems. We will practice modern digital system design by using state of the art software tools and implementation of the digital systems on a programmable hardware platform. At the end of the course, students will be familiar with modern approach for designing digital systems, using hardware description languages along with an appropriate methodology.

Syllabus

Lecture Slides

Autograder (Only accessible within IU)

Piazza

Downloads

Canvas (Registered students only)

Projects

P0 - Vivado Tutorial

P1 - Logic Gates

P2 - Demultiplexer

P3 - ALU

P4 - Countdown Timer

P5 - Elevator Controller

Course Schedule

This is the tentative schedule for this semester.

Date Day Lecture Topic Project Topic
1/8 Tuesday Intro / Logic  
1/10 Thursday Vivado Tutorial Basic Logic Gates
1/15 Tuesday Verilog Basics  
1/17 Thursday Decoders/Encoders Decoder / Demux
1/22 Tuesday Mux/Demux  
1/24 Thursday Adders / ALUs ALU
1/29 Tuesday ALUs / Latches  
1/31 Thursday Latches / Flops Timer
2/5 Tuesday Sequential Logic  
2/7 Thursday Finite State Machines Timer
2/12 Tuesday Finite State Machines  
2/14 Thursday Finite State Machines Elevator Controller
2/19 Tuesday Serial Communication  
2/21 Thursday Review Elevator Controller
2/26 Tuesday Exam I  
2/28 Thursday Serial Communication UART
3/5 Tuesday Serial Communication  
3/7 Thursday Memory UART
3/12 Tuesday Spring Break  
3/14 Thursday Spring Break
3/19 Tuesday Memory  
3/21 Thursday Memory Calculator
3/26 Tuesday CPU Design  
3/28 Thursday CPU Design Calculator
4/2 Tuesday CPU Design  
4/4 Thursday CPU Design CPU
4/9 Tuesday FPGA Internals  
4/11 Thursday FPGA Internals CPU
4/16 Tuesday Circuits  
4/18 Thursday CMOS CPU
4/23 Tuesday Overflow  
4/25 Thursday Review
4/30 Tuesday Final 10.15am - 12.15pm